This invention relates to memory circuitry, and more particularly to the addition of data validation to such circuitry.
Programmable logic devices (“PLDs”) frequently include blocks of memory. A task that may need to be performed using a PLD with such memory is comparison of a data word read from the memory with another data word in the PLD circuitry to determine whether or not the two words are the same (a “hit”) or not the same (a “miss”). The purpose of this may be to “validate” either the word read from the memory or the other word in the PLD circuitry. Such validation is generally assumed to have occurred when the two words are found to be the same (i.e., there is a hit); but as an alternative, validation could instead be set up to require a miss.
Validation is typically performed in a PLD by reading a word from the memory and routing that word to programmable logic circuitry of the PLD. The other word to be compared to the memory word is also routed to that programmable logic circuitry, which has been programmed to perform the required comparison (validation) of the two words. The delay in handling the memory word in this way (e.g., the propagation delay through the routing circuitry from the memory to the programmable logic circuitry) can be undesirable in certain applications. For example, this delay may mean that the results of the validation operation are not available until one or more clock cycles after the clock cycle in which the data is read from the memory. This delay may be unacceptable or at least undesirable in applications such as high-speed data communication.